The present invention relates to a semiconductor integrated circuit used in a sustain circuit of a plasma display apparatus, to a drive circuit, and to a plasma display apparatus using these circuits.
The plasma display panel (PDP) is a self-emitting-type display has excellent visibility, is thin, and is capable of producing a large display at a high speed. Therefore, it is attracting interest as a display panel and as a replacement for a CRT. As the basic configuration of a PDP is disclosed in, for example, EP 1139323A, a detailed description is not give here but only points that directly relate to the present invention are described below.
In the PDP apparatus, it is necessary to apply a voltage of about 200 V, at the maximum, between display electrodes as a high-frequency sustain pulse and the pulse width is about several microseconds in a PDP apparatus that provides a gradated display using a subfield display method. As a PDP apparatus is driven by a signal having a high voltage and a high frequency, the power consumption thereof is generally large and it is required to save power. Therefore, a circuit, which recovers power being applied between electrodes when a sustain pulse is applied to change the polarity of the voltage to be applied to the electrode, is used and the recovered power is utilized for the application of a sustain pulse. In a power recovery circuit, it is important to efficiently carry out recovery and application of power and, in order to realize high power-recovery efficiency, it is necessary to apply a sustain pulse at an optimum timing.
EP 1139323A describes a configuration in which a phase adjustment circuit is provided in a drive circuit for driving an output semiconductor device in a sustain circuit of a plasma display apparatus so that the timing of application of a sustain pulse is adjustable. FIG. 1 is a diagram showing the conventional configuration of a sustain circuit of the plasma display apparatus described in EP 1139323A and FIG. 2 is a diagram showing the operation timing. This circuit is a sustain circuit having a power recovery circuit in which a recovery path through which power is recovered and an application path through which accumulated power is applied are separated. By the way, a circuit for generating signals V1 to V4 is also provided, but is omitted here. Reference symbol Cp denotes a drive capacitor of a display cell formed by the X electrode and the Y electrode of the PDP. The sustain circuit shown in FIG. 1 is a half bridge circuit driven by connecting the output semiconductor devices (transistors) on the high side and the low side in series. The part composed of output semiconductor devices (transistors) 31 and 33, drive circuits 32 and 34, and first and second phase adjustment circuits 51 and 52 is a basic sustain circuit. The part composed of output semiconductor devices (transistors) 37 and 40, drive circuits 38 and 41, third and fourth phase adjustment circuits 53 and 54, inductance elements 35 and 43, a capacitor 39, and diodes 36 and 42 is a power recovery circuit. The signals V1 and V2 are inputted to the drive circuits 32 and 34 via the first and second phase adjustment circuits 51 and 52, respectively, and signals VG1 and VG2 output therefrom are applied to the gates of the output devices (transistors) 31 and 33. Here, an example, in which a power MOSFET is used as an output semiconductor device (hereinafter, referred to only as an output device in some cases), but an IGBT may be used instead of a power MOSFET.
When the signal V1 is at the “high (H)” level, the output device 31 is turned on (brought into conduction), and a signal at the H level is applied to the electrode. At this time, the signal V2 is at the “low (L)” level and the output device is in the off state (state of cutoff). At the same time when the signal V1 changes to the L level and the output device 31 turns off, the signal V2 changes to the H level, the output device 33 turns on, and the ground level is applied to the electrode.
When the power recovery circuit is present, as shown in FIG. 2, at the time of application of a sustain pulse, before the signal V1 changes to H, the signal V2 changes to L and after the output device 33 turns off, the signal V3 changes to H and the output device 40 turns on, and a resonance circuit is formed by the capacitor 36, the diode 42, the inductance 43, and the capacitor Cp, the power stored in the capacitor 39 is supplied to the electrode, and the potential of the electrode is raised. Immediately before the rise in the potential is completed, the signal V3 changes to L and the output device 40 turns on and, further, the signal V1 changes to H and the output device 31 turns on, and thus the potential of the electrode is fixed to Vs. When the application of a sustain pulse is terminated, the signal V1 first changes to L and after the output device 31 turns off, the signal V4 changes to H and the output device 37 turns on, and a resonance circuit is formed by the capacitor 39, the diode 36, the inductance 35, and the capacitor Cp and the power stored in the capacitor Cp is supplied to the capacitor 39, and thus the voltage of the capacitor 39 is raised. Due to this, the power stored in the capacitor Cp is recovered by the capacitor 39 by means of the sustain pulse applied to the electrode. Immediately before the drop in potential of the electrode is completed, the signal V4 changes to L and the output device 37 turns off, further the signal V2 changes to H and the output device 33 turns on, and thus the potential of the electrode is fixed to the ground. During the sustain discharge period, the above-mentioned action is repeated the same number of times as the number of sustain pulses. Due to the configuration described above, the power consumption accompanying the sustain discharge can be reduced.
In the power recovery circuit, it is important to perform recovery and application of power efficiently and it is required to realize a high power recovery efficiency. The power recovery efficiency is affected by the on/off timing of the output devices 31, 33, 37, and 40. FIG. 3A and FIG. 3B are diagrams for explaining this influence, where FIG. 3A shows a case where the timing of clamp is put forward and FIG. 3B shows a case where the timing of clamp is delayed.
As described above, when a sustain pulse is applied, the output device 40 turns on and the power stored in the capacitor 39 is supplied to the electrode, and immediately before the rise in potential of the electrode is completed, the signal V3 changes to L and the output device 40 turns off and at the same time, the signal V1 changes to H and the output device 31 turns on, and thus the potential of the electrode is fixed (clamped) to Vs. Here, as shown in FIG. 3A, if the output device 31 turns on before the output device 40 turns off, the electrode is connected to the power supply of the voltage Vs while the potential of the electrode is being raised by the power stored in the capacitor 39 because the output device 31 turns on, therefore, the rest of the rise process in potential is carried out by the power from the power supply. This means that part of the power stored in the capacitor 39 is wasted. Similarly, when the application of a sustain pulse is completed, if the output device 33 turns on after the output device 37 turns on and while power is being recovered to the capacitor 39, power is not recovered sufficiently because of clamp to the ground before the power is recovered sufficiently.
Moreover, as shown in FIG. 3B, when a sustain pulse is applied, if the output device 31 turns on after the output device 40 turns off, the rise in potential of the electrode is terminated by the power stored in the capacitor 39 and conversely, after the potential of the electrode begins to fall, the output device 31 turns on to clamp the electrode to the power supply of the voltage Vs, therefore, the fallen potential needs to be raised and excessive power is required accordingly. Similarly, when the application of a sustain pulse is completed, if the output device 33 turns on after the output device 37 turns off, because of clamp to the ground after the once fallen potential begins to rise, the raised potential needs to be lowered and excessive power is required accordingly.
As described above, if the timing of turning on/off of the output devices 31, 33, 37, and 40 in the sustain circuit is shifted, there arises a problem in that the power consumption is increased. The timing of turning on/off of the output devices 31, 33, 37, and 40 is the sum of the timing of change of the signals V1, V2, V3, and V4, the delay time of the drive circuits 32, 34, 38, and 41, and the delay time of the output devices 31, 33, 37, and 40. The timing of change of the signals V1, V2, V3, and V4 can be set relatively highly precisely, but the delay time of the drive circuits 32, 34, 38, and 41 and the delay time of the output devices 31, 33, 37, and 40 vary depending on the variations in the characteristics of the devices to be used. Therefore, the power recovery efficiency of PDP apparatuses differ and the power recovery efficiency is degraded compared to an ideal case, and there arises a problem of an increase in power consumption.
Moreover, if the delay time of the circuit element varies and the shape and timing of the sustain pulse differ from each other, the possibility that the normal operation cannot be carried out becomes stronger. Normally, the difference ΔVs of the operation voltage Vs between the maximum voltage Vs (max) and the minimum voltage (min) is referred to as an operation margin, and if the delay time of the circuit element varies and the shape and timing of the sustain pulse differ from each other, the operation margin ΔVs is reduced. This means that the stability of the operation of the apparatus is reduced.
In an ALIS system PDP apparatus to be described later, no discharge is caused to occur between neighboring electrodes to which the same voltage is applied but, if the timing of application is shifted, a discharge is caused to occur temporarily also in a display line that does not serve to provide a display, wall charges written during the address period are reduced, and there arises a problem in that a normal display cannot be provided.
As described above, there has been a problem in that the delay time of each circuit element in the sustain circuit varies and, in accordance with this, the on/off timing of the sustain pulse is shifted and the shape thereof is altered, the power consumption is increased and malfunctions occur.
Therefore, as shown in FIG. 1, in the previous stage of the drive circuits 32, 34, 38, and 41, the first phase adjustment circuit 51, the second phase adjustment circuit 52, the fourth phase adjustment circuit 54, and the third phase adjustment circuit 53 are provided in order to adjust the timing of the change edge of the sustain pulse to an optimum state. Due to this, the power recovery circuit can be operated efficiently, therefore, power consumption can be reduced. Moreover, the on/off timing of the sustain pulse to be applied form each sustain circuit is brought into an optimum condition to each other, therefore malfunctions and erroneous discharges are unlikely to occur.